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ASIC/RTL Design Engineer 4

Skills

Python

Description

Job Description Job Description Job Overview: Requirement/Must Have: Solid understanding of digital design and computer architecture fundamentals.

Hands-on experience with Verilog or SystemVerilog RTL design.

Ability to read, modify, debug, and maintain existing design code.

Familiarity with simulation and debug tools such as VCS, ModelSim, Verdi, waveform viewers, or equivalent tools.

Basic scripting ability in Perl, Tcl, Python, Bash, C-shell, or similar.

Strong analytical skills, attention t…

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