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Design Verification Engineer

Skills

ethernetpcieperlpythonsystemveriloguvmPython

Description

  • Job Title : Design Verification Engineer
  • Client: Arrow Electronics
  • Experience Required: 8 to 15 years only
  • Work Location: San Jose CA (Complete Onsite)
  • Visa: All visa, except H1B transfer
  • C2C engagements are allowed.

We are seeking Design Verification Engineer with exposure on Developing and maintaining UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems)

Key Skill: SV/UVM, PCIe/Ethernet/HBM

What You'll Be Doing:

Strong in SV/UVM scale test bench

AXI expertise, NOC/Crossbar, Performance

Regression/Triage and coverage closure

Need asap → Program has already started and is in execution

Ability to work on Amazon tools, flows, methodology. Work is in start-up mode with less documentation available

What we are looking for:

A bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline.

Verification closure with team

Make/Perl/Python

Ensure customer satisfaction.

Reporting to customer on daily or weekly progress effectively

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