Formal Design Verification Engineer

Job Description

Key Responsibilities:

• • Develop formal verification environments using SystemVerilog modules and SystemVerilog Assertions (SVA).
• • Execute formal verification checks, analyze results, and debug failures to ensure design functionality and correctness.
• • Develop and enhance formal constraints, assertions, checks, and cover properties to improve verification quality and coverage.

• Verify GPU design blocks using formal methodologies, including:

• o Sequential equivalence checking.
• o Property-based feature verification.
• o Datapath equivalence verification using C and RTL models.
• • Develop formal-based datapath verification environments using RTL and C models.
• • Develop and maintain property-based formal verification environments for design features.
• • Perform proof-depth, complexity, and convergence analysis to evaluate formal verification effectiveness.
• • Identify root causes of formal failures and determine whether issues originate from the design, constraints, or verification setup.
• • Apply formal convergence techniques, including abstraction, black-boxing, and design reductions
• • Collaborate with RTL designers to troubleshoot failures and improve formal setups or RTL implementation.
• • Partner with cross-functional teams, including design, architecture, and software engineering, to align verification activities with project goals and requirements.
• • Contribute to the development and continuous improvement of verification methodologies, tools, and workflows.
• • Manage project execution and planning activities using tools such as Confluence and JIRA.
• • Develop and maintain formal verification documentation, including test plans, convergence reports, complexity analysis reports, and verification results.
• • Drive assigned formal verification activities and communicate progress, results, and potential challenges to project verification leads.

Qualifications:

• • Bachelor's degree in Electrical Engineering (BSEE), Computer Engineering, Computer Science, or a related technical discipline.
• • Minimum of 3+ years of relevant engineering experience.
• • Strong understanding of CPU and/or GPU design architecture.
• • Strong experience with SystemVerilog (SV) and SystemVerilog Assertions (SVA) development.
• • Demonstrated hands-on experience developing formal verification environments and setups.
• • Experience analyzing formal verification results, debugging failures, and improving proof convergence.
• • Proficiency working in a Linux environment.
• • Excellent written and verbal communication skills.
• • Ability to collaborate effectively with cross-functional engineering teams.
• Preferred
• • Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• • Experience developing constrained-random testbenches.

• Experience with formal verification tools such as:

• o Synopsys VC Formal
• o Cadence JasperGold
• o Siemens Questa Formal
• • Hands-on experience with formal datapath verification using C and RTL models.
• • Experience with sequential equivalence checking and property-based verification.
• • Strong understanding of formal convergence techniques, proof-depth analysis, abstraction, black-boxing, and design reduction methodologies.
• • Experience working with project management and collaboration tools such as JIRA and Confluence.

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  Saige Partners, one of the fastest growing technology and talent companies in the Midwest, believes in people with a passion to help them succeed. We are in the business of helping professionals Build Careers, Not Jobs. Saige Partners believes employees are the most valuable asset to building a thriving and successful company culture, which is why we offer a benefit package and convenient weekly payment solutions that helps our employees stay healthy and maintain a positive work/life balance. Contact us to learn more about the opportunity below or check out other opportunities at https://careers.saigepartners.com/.