Formal Verification Lead

As a static formal verification lead, you will play a key role in ensuring functional correctness and low-power intent integrity across the design lifecycle.

You will be responsible for equivalence checking with and without UPF, ensuring seamless convergence between RTL, synthesis, and physical design stages for hierarchical designs.

Key

Responsibilities

Perform RTL-to-Gate and Gate-to-Gate equivalence checks using tools like Synopsys Formality Debug LEC failures, including issues arising from …