Functional Verification Engineer
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Description
As a Functional Verification Engineer , you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level.
Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.
The Role Reading and analysing the system
requirements
and architecture requirement documents.
Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++…
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