Lead High-Speed Verification Engineer – PCIe/UCIe
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Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona to lead functional verification of high-speed interface protocol blocks at IP and subsystem levels.
The role blends hands-on verification with technical leadership across RTL, architecture, firmware and verification teams.
You will architect and maintain UVM environments, own verification of PCIe/UCIe/SerDes, and act as protocol expert for AXI, CXS, AHB, CHI.
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