Physical ASIC Design Implementation Engineer
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Description
Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, for toplevel chips aswell as blocklevel blocks in technologies ranging from N2 to 180nm.
This with the full understanding of the complete Cadence Innovus Place&Route flow. *Direct contact with our customers for future projects. *Full understanding of the complete Cadence Innovus Place&Route flow. *Take the lead for partitioning and split the top level SDC file into timing budget
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