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Principal HS Digital Design Engineer (d/m/f)

Skills

cmospciertlsystemverilogverilogNode.js

Description

Who we are looking for

  • MSc or PhD in Electrical Engineering
  • 10+ years digital IC design experience
  • RTL design (Verilog/SystemVerilog)
  • High-speed digital IC design experience for communication or mixed-signal SoC products is required; knowledge of high-speed interfaces such as UCIe, PCIe or similar protocols is an advantage
  • Interface protocols and clock-domain crossing
  • Synthesis and timing analysis
  • Advanced CMOS node experience, including FinFET and/or FD-SOI, is required

Please contact Hana Krsul for further information via [email protected] or +43 664 9665611.

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