Senior ASIC RTL Design Engineer

Pay Range: $89.11hr - $94.06hr Job Overview: In this role, the successful candidate will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs.

The candidate will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product

requirements

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Candidate Profile: The successful candidate is passionate about digital design, power optimization, and timing closure in a…