Senior / Physical Design Engineer

Responsibilities

Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.

Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners.

TOP role for the complicated hierarchical chip (more than 20 Million instances plus 500 macros), doing floorplan and partition, responsible for…