Senior/Principal SoC Verification Engineer — UVM & SystemVerilog

NSING, part of Nations Technologies Group, Singapore, is seeking a SoC Design Verification Engineer to join our Singapore R&D Center.

You will develop verification plans, build test benches with SystemVerilog and UVM, write and debug test cases, analyze coverage, and mentor junior engineers as part of a cross-functional team.

Requirements

include a Bachelor’s or Master’s in Electrical/Computer Engineering and 3 years of industry experience; deep knowledge of digital logic, SOC architecture, J-1…