Senior Verification Engineer, LSU and Data Cache
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Description
Job Description Our partner is looking for a Senior Verification Engineer to own verification of the Load/Store Unit, data cache and related bus interfaces within a processor core.
The role covers memory ordering, cache and TLB interaction, address generation, forwarding, speculative execution, vector accesses, exceptions and pipeline hazards.
You will own the verification scope from planning through sign off, working closely with architecture, RTL and other verification teams.
Location: Barcel…
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