Staff Analog Mixed-Signal Circuit Design Engineer

1.

Advanced CMOS PLL architecture definition, device level design and verification.

3.

Lead layout implementation and testing.

4.

Achieve industry leading jitter, noise and spur performance.

5.

Architecture and system level design.

Architecture choice-based noise/jitter/spur spec (optimal architecture - integer/Fraction/SS/MDLL etc.) Derive system parameters (Loop BW, Noise margin, noise TF, spur reduction), system verification through behavioral to transistor model (Verilog-A, MATLAB, SpectreR…